I. What is packaging.
Plan implies that the circuit pins on the silicon wafer are connected to the outside adapter with cords to get in touch with other tools. Plan form describes setting up semiconductor integrated circuit chips with the covering. It plays a role in the installation, fixation, sealing, and defense of the chip. It enhances the electrical and thermal buildings through the get in touches with on the chip with wires connected to the pins of the plan covering. These pins are attached to other tools with the cables on the printed circuit board to attach the interior chip and also the outside circuit. The fragment must be separated from the outside world to avoid corrosion and air impurities as well as cause electrical degradation on the chip circuit.
On the various other hand, the encapsulated chip is likewise simpler to set up and carry. As the product packaging technology is also directly affected by the chip itself as well as the efficiency of the PCB (printed circuit card) attached to the layout as well as manufacture, it is therefore important.
An important indicator to gauge the sophisticated modern technology of a chip package is the proportion of chip area to package area. The closer the balance is to 1, the far better. The main factors to consider when product packaging.
the proportion of chip area to package area to improve the efficiency of the package, as close to 1:1.
the pins should be as brief as possible to decrease the delay as well as the range between the pins as far as feasible to ensure that they do not interfere with each other to improve efficiency.
based on the heat dissipation needs, the thinner the bundle, the much better.
The bundle is mostly divided into 2 DIP double inline and also SMD plans. From the structural facet, the plan has established from the earliest transistor TO (such as TO-89, TO92) bundle to the dual inline bundle, complied with by the advancement of the SOP tiny type factor bundle by PHILIP, and then slowly obtained SOJ (J-type pin little type element plan), TSOP (thin little type aspect plan), VSOP (small form aspect package), SSOP (lowered SOP), TSSOP (thin decreased SOP) as well as SOT (little form aspect transistor), SOIC (small type factor incorporated circuit), and so on. From the material tool, consisting of metal, ceramic, plastic, as well as plastic, lots of high-intensity working conditions demanded by the program, such as armed forces and also aerospace degrees, still have numerous metal plans.
Packaging has actually generally undergone the adhering to growth procedure.
Structure: TO- > DIP- > PLCC- > QFP- > BGA- > CSP.
Products: steel, ceramic -> ceramic, plastic -> plastic.
Pin shape: long-lead straight insert -> short-lead or leadless place -> sphere bumps.
Assembly setting: through-hole cartridge -> surface setting up -> direct installing
The 2nd is the certain package type.
1 、 SOP/ SOIC plan
SOP is the acronym of Small Overview Plan, a tiny rundown plan SOP bundle technology was established successfully by Philips in 1968-1969, and afterwards gradually obtained SOJ (J-type pin small summary plan), TSOP (thin small overview bundle), VSOP (really little summary plan), SSOP (reduced SOP), TSSOP (thin decreased SOP) as well as SOT. (tiny kind aspect SOP) and SOT (small type aspect transistor), SOIC (tiny form aspect integrated circuit), and so on 2 、 DIP package
DIP is the acronym of Double Inline Bundle, that is, double inline plan DIP is just one of one of the most preferred plug-in plans. The application array consists of standard logic IC, memory LSI, microcomputer circuits, etc 3 、 PLCC package.
PLCC is the acronym of Plastic Leaded Chip Provider, a plastic J-lead chip bundle. PLCC bundle, square form, 32-pin package, bordered by pins, the form aspect is a lot smaller than the DIP bundle. The PLCC package is suitable for placing and also electrical wiring on PCB with SMT surface mount innovation as well as has the benefits of a tiny form variable and also high integrity.
2、 TQFP bundle.
TQFP is the acronym of the slim quad flat plan, that is, the thin plastic sealed quad well balanced package. The thin quad flat plan (TQFP) process makes reliable use of room, consequently lowering the dimension of the printed circuit board area needs. As a result of the minimized height and also dimension, this packaging procedure is optimal for space-critical applications such as PCMCIA cards and also networking tools. Almost all of ALTERA's CPLD/FPGAs are offered in TQFP plans.
3、 PQFP Package
PQFP is the acronym of Plastic Quad Flat Package. The distance in between the chip's pins in the PQFP package is very tiny, and also the pins are very slim. Typically, massive or incredibly large-scale incorporated circuits utilize this bundle type. The variety of pins is generally above 100.
4、 TSOP plan
TSOP is the abbreviation of Thin Small Summary Package, a slim tiny size bundle A common function of TSOP memory packaging innovation is to make pins around the packaged chip. TSOP is suitable for SMT modern technology (surface place technology) in the PCB (printed circuit board) to install circuitry. TSOP package type factor, parasitical criteria (current When the TSOP plan type aspect, the parasitic specifications (result voltage disruption brought on by substantial modifications) are lowered, ideal for high-frequency applications, easier to run, and also extra trustworthy.
5、 BGA package.
BGA is the acronym of Sphere Grid Selection Plan. 20 **** 90s, with the progression of innovation, chip assimilation remains to enhance, the variety of I/O pins enhanced sharply, power intake additionally raised, and the demands of integrated circuit product packaging are additionally much more rigid. BGA bundles started to be utilized in production to satisfy the advancement needs.
Memory packaged with BGA technology can raise memory capability by a couple of times with the very same memory volume. BGA has a smaller sized dimension, much better thermal efficiency, and electrical performance than TSOP. BGA packaging modern technology has actually led to a considerable boost in storage space capability per square inch. Memory products using BGA product packaging modern technology are just one-third the dimension of TSOP packaging for the very same power. Additionally, the BGA packaging technique has a much faster and also more effective means of dissipating warm than the standard TSOP product packaging method.
The benefits of BGA modern technology are that although the variety of I/O pins has raised, the pin spacing has enhanced instead of lowering, thus enhancing the setting up yield; although its power intake has actually raised, BGA can be soldered with the controlled collapse chip approach, therefore boosting its electric as well as thermal efficiency; the thickness as well as weight have been reduced contrasted to the previous packaging Although its power usage boosts, BGA can be soldered with regulated collapse chip approach, which can boost its electrical and thermal performance; density and also weight are decreased compared with previous product packaging modern technology; parasitic specifications are lowered, signal transmission hold-up is small, and also frequency of usage is substantially enhanced; assembly can be soldered with the common surface, which is extremely reliable.
Relating to the BGA package, Kingmax's copyrighted TinyBGA modern technology must be discussed. It was developed by Kingmax in August 1998 and has a chip location to package location ratio of not less than 1:1.14, which can boost memory ability by 2 to 3 times with the very same volume of memory, as well as has a smaller sized size, better thermal efficiency, and electrical efficiency contrasted to TSOP plan items.
The TSOP bundle memory pins are led from all over the chip, while the TinyBGA is revealed from the facility of the chip. This technique successfully reduces the signal conduction range, with signal transmission lines just 1/4 the size of standard TSOP innovation, and consequently signal attenuation is decreased. This substantially boosts the chip's anti-interference and also anti-noise efficiency and improves the electrical efficiency. The TinyBGA bundle chip is immune to outside regularities as much as 300MHz, while the conventional TSOP package innovation is just resistant to outside regularities as much as 150MHz.
The TinyBGA package is also thinner (package elevation is much less than 0.8 mm), and the effective heat dissipation course from the metal substratum to the warmth sink is just 0.36 mm. Consequently, TinyBGA memory has greater thermal conductivity as well as is optimal for systems that run for long periods with superb stability.
Three, several of the worldwide brand names of products plan naming regulations information
1. MAXIM is prefixed with "MAX," while DALLAS begins with "DS.".
MAX × × × × or MAX × × × ×.
Summary: 1.
1, suffix CSA, CWA where C means regular degree, S means table sticker, as well as W implies wide-body table sticker.
2, suffix CWI suggests large body table sticker, EEWI wide body industrial-grade table sticker, suffix MJA or 883 for a military-grade.
3, CERTIFIED PUBLIC ACCOUNTANT, BCPI, BCPP, CPP, CCPP, CPE, CPD, as well as ACPA suffix are ordinary double inline plugs.
Instances MAX202CPE, CPE average ECPE normal with antistatic protection, MAX202EEPE industrial-grade antistatic security (-45 ℃ -85 ℃), showing that E describes antistatic defense proverb electronic arrangement category.
1-character analog 2-character filter 3-character multiplexer.
4 head amplifier 5 head digital-to-analog converter 6 head voltage reference.
7-word voltage converter, 8-word reset, 9-word comparator.
DALLAS Naming Rules.
For example, DS1210N.S. DS1225Y-100IND.
N= commercial quality S= Sheeted vast body MCG= DIP secured Z= Sheeted vast body MNG= DIP commercial quality.
IND= industrial grade QCG= PLCC Q= QFP.
2 、 AD items are mostly "ADVERTISEMENT" and also "ADV", however also "OP" or "REF", "AMP" and also "AMP". "AMP", "SMP", "SSM", "TMP", "TMS", and so on "TMS" and more.
Description of suffixes.
1 、 J in the suffix means a civil product (0-70 ℃), N suggests regular plastic seal, as well as R in the suffix implies table sticker.
2, suffix with D or Q shows the ceramic seal, commercial grade (45 ℃ -85 ℃). H in the suffix indicates rounded cap.
3, SD or 883 in the suffix is an army product.
As an example, JN DIP bundle JR table sticker JD DIP ceramic seal.
4, BB product calling guidelines.
Prefix ADS analog tools Suffix U table sticker P is DIP package with B shows industrial-grade Prefix INA, XTR, PGA, etc shows high-precision op-amp Suffix U table sticker label P represents DIP PA suggests high-precision.
4 、 INTEL item calling policies.
N80C196 series are single-chip.
Prefix: N = PLCC bundle T = industrial quality S = TQFP package P = DIP package.
KC20 main regularity KB main frequency MC represents 84 lead angle.
Example: TE28F640J3A-120 Flash TE= TSOP DA= SSOP E= TSOP.
5 、 Beginning with "IS.".
For example, IS61C IS61LV 4 × means DRAM 6 × means SRAM 9 × indicates EEPROM.
Plan: PL= PLCC PQ= PQFP T= TSOP TQ= TQFP.
6 、 LINEAR is prefixed with the item name.
LTC1051CS CS suggests table sticker label.
LTC1051CN8 ** indicates * IP plan 8-pin.
7 、 IDT's items are generally IDT beginning.
Suffix summary.
1, the suffix TP is a narrow body DIP.
2, suffix P belongs to the large body DIP.
3, suffix J comes from PLCC.
For example, IDT7134SA55P is a DIP bundle.
IDT7132SA55J is PLCC.
IDT7206L25TP is DIP.
8 、 NS products component of the beginning of the LM, LF.
LM324N 3 characters on behalf of the private items with N round cap.
LM224N 2 personalities in behalf of industrial-grade with J ceramic seal.
LM124J 1 personalities in support of army products with N plastic seal.
9 、 HYNIX.
Package: DP stands for DIP package, DG stands for SOP plan, DT stands for TSOP plan.
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